The present invention relates generally to the field of nanotechnology. More specifically, the invention provides a method and system based on field effect transistors for addressing nanometer-scale devices. Merely by way of example, the invention has been applied to nanometer-scale wires, but it would be recognized that the invention has a much broader range of applicability.
In the field of nanotechnology, it is important to bridge the length scales between the ultra-high density patterns achievable through nanometer-dimension patterning techniques, and the patterns that are achievable using lithographic patterning techniques. The nanometer-scale patterning techniques may use self-assembly processes and/or non-lithographic processes. For example, aligned circuits include nanowires whose diameters are as small as 8 nanometers, and the separations between adjacent nanowires are 16 nm. In contrast, the high resolution lithography technique such as electron-beam lithography (EBL) can make small metal islands as small as 8 nanometers, but those features are usually separated by 60 nanometers or so. For straight and aligned wires, EBL can provide patterns with wire diameters ranging from 20 to 30 nanometers and wire pitches ranging from 60 to 80 nanometers. The wire pitches are related to the separations between adjacent wires. Hence, both the wire diameters and wire pitches from EBL are significantly larger than the diameters and separations of the nanowires.
To bridge the length scales between the nanometer-dimension patterning techniques and lithographic patterning techniques, diode-based binary tree multiplexers-may be used. FIG. 1 is a simplified conventional binary tree multiplexer. The binary tree multiplexer 100 includes nanowires 110 and address wires 120. For example, the address wires 120 are patterned with lithographic techniques and connected with the nanowires 110 with diodes or switches that change between two resistance states includes one of high resistance and the other one of low-resistance. The inputs of the address wires 120 act as the inputs to a logical AND gate. As shown in FIG. 1, 16 nanowires 110 are addressed using 8 address wires 120. This corresponds to 24 nanowires being addressed with 2×4 address wires. Specifically, two address wires 130 are connected to different groups of 8 adjacent nanowires, another two address wires 132 are connected to different groups of 4 adjacent nanowires, yet another two address wires 134 are connected to different groups of 2 adjacent nanowires, and yet another two address wires 136 are connected to different individual nanowires. The topmost nanowire and the bottommost nanowire are considered to be adjacent. Each of the address wires 110 is connected to a different half of the nanowires 120. For example, if the four address wires 140 are grounded, and a voltage is applied to the other four address wires 150, only one nanowire 160 should be connected to all four address wires 150. Hence the nanowire 160 is the wire that is addressed. The binary tree multiplexer 100 may consume significant power and involve complicated fabrication processes.
Hence it is desirable to improve techniques for addressing nanometer-scale devices.